Write RTL for 8:3 priority encoder using structural model.
RTL
// priority circuit
module priorityckt(i0,i1,i2,i3,i4,i5,i6,i7,h0,h1,h2,h3,h4,h5,h6,h7,idle);
input i0,i1,i2,i3,i4,i5,i6,i7;
output h0,h1,h2,h3,h4,h5,h6,h7,idle;
assign h7=i7;
assign h6=i6 & (~i7);
assign h5=i5 & (~i6) & (~i7);
assign h4=i4 & (~i5) & (~i6) & (~i7);
assign h3=i3 & (~i4) & (~i5) & (~i6) & (~i7);
assign h2=i2 & (~i3) & (~i4) & (~i5) & (~i6) & (~i7);
assign h1=i1 & (~i2) & (~i3) & (~i4) & (~i5) & (~i6) & (~i7);
assign h0=i0 & (~i1) & (~i2) & (~i3) & (~i4) & (~i5) & (~i6) & (~i7);
assign idle=(~i0) & (~i1) & (~i2) & (~i3) & (~i4) & (~i5) & (~i6) & (~i7);
endmodule
// binary encoder
module binaryenco(i0,i1,i2,i3,i4,i5,i6,i7,y1,y2,y3);
input i0,i1,i2,i3,i4,i5,i6,i7;
output y1,y2,y3;
assign y1=i1 | i3 | i5 | i7;
assign y2=i2 | i3 | i6 | i7;
assign y3=i4 | i5 | i6 | i7;
endmodule
//8:3 priority encoder structural model
module eto3prioencoder(i0,i1,i2,i3,i4,i5,i6,i7,y0,y1,y2,idle);
input i0,i1,i2,i3,i4,i5,i6,i7;
output y0,y1,y2,idle;
wire w1,w2,w3,w4,w5,w6,w7,w8,w9;
priorityckt P(.i0(i0),.i1(i1),.i2(i2),.i3(i3),.i4(i4),.i5(i5),.i6(i6),.i7(i7),.h0(w1),.h1(w2),.h2(w3),.h3(w4),.h4(w5),.h5(w6),.h6(w7),.h7(w8),.idle(w9));
binaryenco B(.i0(w1),.i1(w2),.i2(w3),.i3(w4),.i4(w5),.i5(w6),.i6(w7),.i7(w8),.y1(y0),.y2(y1),.y3(y2)) ;
assign idle=w9;
endmodule
Test Bench
// 8:3 priority encoder test bench
module eto3prioencoder_tb();
integer i;
reg i0,i1,i2,i3,i4,i5,i6,i7;
wire y0,y1,y2,idle;
eto3prioencoder A(.i0(i0),.i1(i1),.i2(i2),.i3(i3),.i4(i4),.i5(i5),.i6(i6),.i7(i7),.y0(y0),.y1(y1),.y2(y2),.idle(idle));
initial
begin
i0=1'b0;
i1=1'b0;
i2=1'b0;
i3=1'b0;
i4=1'b0;
i5=1'b0;
i6=1'b0;
i7=1'b0;
end
initial
begin
for(i=0;i<256;i=i+1)
begin
{i0,i1,i2,i3,i4,i5,i6,i7}=i;
#5;
end
end
initial
$monitor("Input i0=%b,i1=%b,i2=%b,i3=%b,i4=%b,i5=%b,i6=%b,i7=%b , Output y0=%b,y1=%b,y2=%b,idle=%b",i0,i1,i2,i3,i4,i5,i6,i7,y0,y1,y2,idle);
initial
#1400 $finish;
endmodule
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