Write RTL for 4x1 Mux using Decoder & tri-state buffers and verify the same using a Testbench.

  

Write RTL for 4x1 Mux using Decoder & tri-state buffers and verify the same using a

Testbench.

RTL

//2:4 decoder dataflow level or RTL code

 

module decoder(s0,s1,d0,d1,d2,d3);

 

            input s0,s1;

            output d0,d1,d2,d3;

           

            assign d0=(~s0)&(~s1);

            assign d1=(~s0)&(s1);

            assign d2=(s0)&(~s1);

            assign d3=(s0)&(s1);

     

endmodule

 

//4:1 mux using decoder and tristate buffer

 

module f21mux_d_t(S0,S1,i0,i1,i2,i3,y);

 

      input S0,S1,i0,i1,i2,i3;

      output y;

      wor p;

     

      decoder A(.s0(S0),.s1(S1),.d0(I0),.d1(I1),.d2(I2),.d3(I3));

     

      bufif1 b1(p,i0,I0);

      bufif1 b2(p,i1,I1);

      bufif1 b3(p,i2,I2);

      bufif1 b4(p,i3,I3);

 

      assign y=p;

     

endmodule

 

 

 

 

 

 

 

 

 

 

 

 

 

Test Bench

//421 mux decoder and tristate buff test bench

 

module f21mux_d_t_tb();

 

      reg i0,i1,i2,i3,s0,s1;

      wire y;

     

      integer i;

     

      f21mux_d_t A(.S0(s0),.S1(s1),.i0(i0),.i1(i1),.i2(i2),.i3(i3),.y(y));

     

            initial

                  begin

                        i0=1'b0;

                        i1=1'b0;

                        i2=1'b0;

                        i3=1'b0;

                        s0=1'b0;

                        s1=1'b0;

                  end

           

            initial

                  begin

                        for(i=0;i<64;i=i+1)

                              begin

                                    {i0,i1,i2,i3,s1,s0}=i;

                                    #5;

                              end

                  end

            initial

              $monitor("Input i0=%b, i1=%b, i2=%b, i3=%b, s0=%b, s1=%b, Output y =%b",i0,i1,i2,i3,s0,s1,y);

            initial

            #350

              $finish;

           

endmodule

 

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