Write RTL And Test bench For gated sr latch.

  RTL

//gated latch

 

module gatedlatch(s,r,ctr,q,q_bar);

 

input s,r,ctr;

inout q,q_bar;

wire w1,w2;

 

nand N1(w1,s,ctr);

nand N2(w2,ctr,r);

nand N3(q,w1,q_bar);

nand N4(q_bar,q,w2);

 

endmodule

TEST BENCH

//gated latch tb

 

module gatedlatch_tb();

 

reg r,s,clk;

wire q,q_bar;

//integer i;

 

gatedlatch G(s,r,ctr,q,q_bar);

 

/*initial

        begin

            for(i=0;i<8;i=i+1)

            begin  

                {ctr,s,r}=i;

                #5;

            end

        end

        */

   

initial

        begin

           

            #5 ctr=0; s=0; r=0;

            #5 ctr=0; s=0; r=1;

            #5 ctr=0; s=1; r=0;

            #5 ctr=0; s=1; r=1;

           

           

            #5 ctr=1; s=0; r=0;

            #5 ctr=1; s=0; r=1;

            #5 ctr=1; s=1; r=0;

            #5 ctr=1; s=1; r=1;

            #5 ctr=1; s=0; r=0;

            #5 ctr=1; s=1; r=0;

            #5;

        end

initial

$monitor("Input ctr=%b,s=%b,r=%b, Output q=%b, q_bar=%b",ctr,s,r,q,q_bar);

 

initial

#60 $finish;

endmodule

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