Write RTL And test bench for 2 to 14 updown counter.

  RTL

//2-14 up-down counter

 

module t24_up_down(clk,rst,din,load,ctrl,count);

 

parameter N=4;

 

input clk,rst,load,ctrl;

input [N-1:0]din;

output reg [N-1:0]count;

 

always@(posedge clk)

 

begin

    if(rst)

    count<=2;

   

    else if(load && din<=14 && din>=2)

    count<=din;

   

    else

    begin

    case(ctrl)

   

    2'b0 :  begin

                if(count==14)

                count<=2;

                else

                count<=count+1;

            end

           

    2'b1 :  begin

                if(count==2)

                count<=14;

                else

                count<=count-2'b1;

            end

    endcase

    end

 

end

 

endmodule

 

TEST BENCH 

//2 to 14 up down tb

 

module t24_up_down_tb();

 

reg clk,rst,load,ctrl;

reg [3:0]din;

wire [3:0]count;

 

t24_up_down d(clk,rst,din,load,ctrl,count);

 

initial

    begin

    clk=0;

    forever #5 clk=~clk;

    end

 

task initialize;

begin

{clk,rst,load,ctrl,din}=0;

end

endtask

 

 

task reset;

begin

        @(negedge clk)

        rst=1'b1;

        @(negedge clk)

        rst=1'b0;

end

endtask

 

task  data;

input [3:0]a;

begin

    @(negedge clk)

    load=1'b1;

    din=a;

    @(negedge clk)

    load=1'b0;

end

endtask

 

task control;

input c;

begin

    @(negedge clk)

    ctrl=c;

end

endtask

  

initial

begin

 

initialize;

reset;

control(0);

 

data(4'd15);

 

repeat(15)

    @(negedge clk)

 

#5;

data(4'd3);

 

repeat(15)

    @(negedge clk)

 

#5;

control(1);

data(4'd1);

 

repeat(15)

    @(negedge clk)

 

#5;

data(4'd12);

 

repeat(15)

    @(negedge clk)

 

#5;

data(4'd4);

 

end

 

initial

$monitor("Input rst=%b,clk=%b,din=%b,load=%b Output count=%b",rst,clk,din,load,count);

 

initial

#1500 $finish;

 

endmodule

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