Write rtl to design a 4 bit loadable binary synchronous up-down counter.
RTL
//synchronus up down and loadabe up counter
module sync_up_down_load_counter(clk,load,rst,ctrl,din,count);
parameter N=4;
input clk,rst,load,ctrl;
input [N-1:0]din;
output reg [N-1:0]count;
always@(posedge clk)
begin
if(rst)
count<=0;
else if (load)
count<=din;
else
begin
case(ctrl)
1'b0:count<=count+1;
1'b1:count<=count-1;
endcase
end
end
endmodule
Test bench
//synchronus and loadabe up counter
module sync_up_down_load_counter_tb();
reg rst,clk,load,ctrl;
reg [3:0]din;
wire [3:0]count;
sync_up_down_load_counter SA(clk,load,rst,ctrl,din,count);
initial
begin
clk=0;
forever #5 clk=~clk;
end
task initiaize();
begin
#5;
rst=0;
clk=0;
load=0;
din=0;
end
endtask
task reset();
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask
task data(input [3:0]a);
begin
@(negedge clk)
load=1;
din=a;
@(negedge clk)
load=0;
end
endtask
task control(c);
begin
@(negedge clk)
ctrl=c;
end
endtask
initial
begin
initiaize;
reset;
control(0);
repeat(17)
@(negedge clk)
#5;
data(4'd18);
repeat(17)
@(negedge clk)
#5;
data(4'd5);
control(1);
repeat(17)
@(negedge clk)
#5;
data(4'd17);
repeat(17)
@(negedge clk)
#5;
data(4'd5);
end
initial
$monitor("Input rst=%b,clk=%b,din=%b,load=%b Output count=%b",rst,clk,din,load,count);
initial
#1500 $finish;
endmodule
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