Write RTL And Test bench Code For N-bit Ring Counter

 RTL

//ring counter

 

module ring_counter(rst,clk,q);

 

parameter N=4;

input rst,clk;

output reg [N-1:0]q;

 

 

always @(posedge clk)

begin

       if(rst)

            q<=4'b1000;

        else

            begin

                q<={q[0],q[N-1:1]};

            end

end

endmodule

 

 

TEST BENCH

//ring counter test bench

 

module ring_counter_tb();

 

reg rst,clk;

wire [3:0]q;

 

 

ring_counter RC(rst,clk,q);

 

initial

    begin

    clk=0;

    forever #5 clk=~clk;

    end

 

task initiaize();

    begin

        #5;

        rst=0;

        clk=0;

    end

endtask

 

task reset();

    begin  

    @(negedge clk)

    rst=1'b1;

    @(negedge clk)

    rst=1'b0;

    end

endtask

 

 

initial

begin

    initiaize;

    reset;

       

    #25;

    reset

   

    #25;

end

 

initial

$monitor("Input rst=%b,clk=%b, Output q=%b",rst,clk,q);

 

initial

#250 $finish;

 

endmodule

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