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Design a synchronous logic control unit for Vending machine. Write RTL and testbench.

 The machine can take only two types of coins of denomination l' arid 2 in any order. It delivers only one product that is priced Rs. 3. On receiving Rs. 3, the product is delivered by asserting an Output I which otherwise remains 0. If it gets Rs_ 4, then the product is delivered by asserting X and also a coin return mechanism is activated by output Y = I to return a Re. I coin. There are two sensors to sense the denomination of the coins that give binary output as shown in the following table. The clock speed is much higher than human response time, i.e. no two coins can be deposited in same clock cycle.

 

i

j

coin

0

x

No coin drop

1

0

One rupee

1

1

Two rupee

 

RTL

/*vending machin moore model style -3

coin=0,1(0x)--> no coin

coin=2(10) --> 1 rs;

coin=3(11) --> 2 rs;

*/

 

module vending(clk,rst,coin,p,r);

 

input clk,rst;

input [1:0]coin;

output reg p,r;

 

reg [1:0]state,next_state;

 

parameter s0=2'b00,s1=2'b01,s2=2'b10;

 

always@(posedge clk)

begin

    if(rst)

    state<=s0;

    else

    state<=next_state;

end

 

always@(*)

begin

    next_state=s0;

    case(state)

   

    s0  : if(coin==2)

            next_state=s1;

          else if(coin==3)

            next_state=s2;

   

    s1  : if(coin==2)

            next_state=2;

          else if(coin==3)

            next_state=s0;

          else

            next_state=s1;

               

    s2  : if(coin==2 || coin==3)

            next_state=s0;

          else

            next_state=s2;

    endcase

end

 

always@(posedge clk)

    begin

        p<=0;

        r<=0;

       

        case(state)

       

        s1 : if(coin==3)

                p<=1;

       

        s2 : if(coin==2)

                p<=1;

             else if(coin==3)

             begin

                p<=1;

                r<=1;

             end

       

        endcase

    end

   

 

endmodule

 

 

Test Bench

//fsm overlapping sequence ditector test bench

 

 

module vending_tb();

       

  

reg  clk,rst;

reg [1:0]coin;

wire p,r;

           

   

  

vending V(clk,rst,coin,p,r);

 

 

initial

    begin

     clk=0;

     forever #5 clk=~clk;

    end

   

 

task initialize( );

    begin

      coin = 0;

    end

endtask

  

task reset();

    begin

     @(negedge clk)

     rst=1'b1;

     @(negedge clk)

     rst=1'b0;

    end

endtask

       

  

task stimulus(input [1:0]paisa);

    begin

       @(negedge clk);

       coin=paisa;

    end

endtask             

 

               

initial

    begin

    initialize;

    reset;

    stimulus(2);

    stimulus(2);

    stimulus(3);

    #5;

    reset;

    stimulus(2);

    stimulus(3);

    stimulus(3);

    stimulus(1);

    stimulus(0);

    stimulus(2);

    stimulus(3);

   

      

    $finish;

    end

           

 initial

      $monitor("clk=%b,rst=%b, coin=%b Output p=%b, r=%b",clk,rst,coin,p,r);

     

endmodule    

 

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  E-Mail:-denilvaghasiya17@gmail.com


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