Go to part ----> part 1 part 3 part 4 part 5
3>Alarm Register
As we know register is use for load the value / store the value right?
This Alarm register is same as what you think ..
If load new a ==1 then it is load all new alarm value to alarm time respectivally
other wise it hold value.
RTL
//alarm register
module alarmregister(clk,rst,load_new_a,
new_alarm_ms_hr,new_alarm_ls_hr,new_alarm_ms_min,new_alarm_ls_min,
alarm_time_ms_hr,alarm_time_ls_hr,alarm_time_ms_min,alarm_time_ls_min);
input clk,rst,load_new_a;
input [3:0]new_alarm_ms_hr,new_alarm_ls_hr,new_alarm_ms_min,new_alarm_ls_min;
output reg [3:0]alarm_time_ms_hr,alarm_time_ls_hr,alarm_time_ms_min,alarm_time_ls_min;
always@(posedge clk)
begin
if(rst)
begin
alarm_time_ms_hr<=0;
alarm_time_ls_hr<=0;
alarm_time_ms_min<=0;
alarm_time_ls_min<=0;
end
else if(load_new_a)
begin
alarm_time_ms_hr<=new_alarm_ms_hr;
alarm_time_ls_hr<=new_alarm_ls_hr;
alarm_time_ms_min<=new_alarm_ms_min;
alarm_time_ls_min<=new_alarm_ls_min;
end
else
begin
alarm_time_ms_hr<=alarm_time_ms_hr;
alarm_time_ls_hr<=alarm_time_ls_hr;
alarm_time_ms_min<=alarm_time_ms_min;
alarm_time_ls_min<=alarm_time_ls_min;
end
end
endmodule
TEST BENCH
//alarm register test bench
module alarmregister_tb();
reg clk,rst,load_new_a;
reg [3:0]new_alarm_ms_hr,new_alarm_ls_hr,new_alarm_ms_min,new_alarm_ls_min;
wire [3:0]alarm_time_ms_hr,alarm_time_ls_hr,alarm_time_ms_min,alarm_time_ls_min;
alarmregister AR(clk,rst,load_new_a,
new_alarm_ms_hr,new_alarm_ls_hr,new_alarm_ms_min,new_alarm_ls_hr,
alarm_time_ms_hr,alarm_time_ls_hr,alarm_time_ms_min,alarm_time_ls_min);
initial
begin
clk=0;
forever #5 clk=~clk;
end
task initialize();
begin
{clk,rst,load_new_a,new_alarm_ms_hr,new_alarm_ls_hr,new_alarm_ms_min,new_alarm_ls_hr}=0;
end
endtask
task reset();
begin
@(negedge clk)
rst=1;
@(negedge clk)
rst=0;
end
endtask
task data(input [3:0]a,b,c,d);
begin
@(negedge clk)
load_new_a=1;
new_alarm_ms_hr=a;
new_alarm_ls_hr=b;
new_alarm_ms_min=c;
new_alarm_ls_min=d;
@(negedge clk)
load_new_a=0;
end
endtask
initial
begin
initialize;
reset;
data(4'd1,4'd2,4'd3,4'd0);
repeat(4)
@(negedge clk)
data(4'd2,4'd3,4'd4,4'd5);
repeat(4)
@(negedge clk)
#5;
end
initial
$monitor("Input clk=%b,rst=%b,new_alarm_ms_hr=%b,new_alarm_ls_hr=%b,new_alarm_ms_min=%b,new_alarm_ls_min=%b Output alarm_time_ms_hr=%b,alarm_time_ls_hr=%b,alarm_time_ms_min=%b,alarm_time_ls_min=%b",clk,rst,new_alarm_ms_hr,new_alarm_ls_hr,new_alarm_ms_min,new_alarm_ls_min,alarm_time_ms_hr,alarm_time_ls_hr,alarm_time_ms_min,alarm_time_ls_min);
initial
#100 $finish;
endmodule
________________--> Continue with project(part 3)part 3
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