write rtl description and testbench for a 4bit synchronous and loadable binary up counter.

RTL

//synchronus and loadabe up counter

 

module sync_up_load_counter(clk,load,rst,din,count);

 

parameter N=4;

input clk,rst,load;

input [N-1:0]din;

output reg [N-1:0]count;

 

always@(posedge clk)

    begin

            if(rst)

            count<=0;

           

            else if (load)

            count<=din;

           

            else

                count<=count+1;

               

    end

endmodule

 

Test bench

////synchronus and loadabe up counter

 

module sync_up_load_counter_tb();

 

reg rst,clk,load;

reg [3:0]din;

wire [3:0]count;

 

 

sync_up_load_counter SA(clk,load,rst,din,count);

initial

    begin

    clk=0;

    forever #5 clk=~clk;

    end

 

task initiaize();

    begin

        #5;

        rst=0;

        clk=0;

        load=0;

        din=0;

    end

endtask

 

task reset();

    begin  

    @(negedge clk)

    rst=1'b1;

    @(negedge clk)

    rst=1'b0;

    end

endtask

 

 

task data(input [3:0]a);

    begin

        @(negedge clk)

        load=1;

        din=a;

        @(negedge clk)

        load=0;

    end

endtask

 

initial

begin

    initiaize;

    reset;

    repeat(16)

    @(negedge clk)

       

    #5;

    data(4'd4);

   

    repeat(16)

    @(negedge clk)

   

    #5;

    data(4'd17);

end

 

initial

$monitor("Input rst=%b,clk=%b,din=%b,load=%b Output count=%b",rst,clk,din,load,count);

 

initial

#500 $finish;

 

endmodule

 


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