Write Rtl to design a 16x8 synchronous dual port ram & verify the same.
RTL
//ram
module ram_sync(clk,rst,we,re,w_add,data_in,r_add,data_out);
parameter depth=16;
parameter widht=8;
parameter addr_size=4;
integer i;
input clk,rst,we,re;
input [addr_size-1:0]w_add,r_add;
input [widht-1:0]data_in;
output reg [widht-1:0]data_out;
reg [widht-1:0] mem[depth-1:0];
always@(posedge clk)
begin
if(rst)
begin
for(i=0;i<depth;i=i+1)
begin
mem[i]<=0;
data_out<=0;
end
end
else
begin
if(we)
mem[w_add]<=data_in;
else if(re)
data_out<=mem[r_add];
end
end
endmodule
Test Bench
//syncronus dual port ram tb
module ram_sync_tb();
reg clk,rst;
wire [7:0] data_out;
reg [3:0] w_add,r_add;
reg we,re;
reg [7:0] data_in;
ram_sync R(clk,rst,we,re,w_add,data_in,r_add,data_out);
initial
begin
clk=0;
forever #5 clk=~clk;
end
task initialize();
begin
we=1'b0;
re=1'b0;
rst=1'b0;
data_in=0;
w_add=0;
r_add=0;
end
endtask
task reset;
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask
task write(input w,r, input [3:0]a,input [7:0]b);
begin
@(negedge clk)
begin
we=w;
re=r;
w_add = a;
data_in = b;
end
end
endtask
task read(input w,r, input [3:0]a);
begin
@(negedge clk)
begin
we=w;
re=r;
r_add = a;
end
end
endtask
initial
begin
initialize;
reset;
repeat(10)
write(1'b1,1'b0,(({$random}%8)+1'b1),(({$random}%256)+1'b1));
repeat(10)
read(1'b0,1'b1,({$random}%8));
#100 $finish;
end
initial
$monitor("Values of clk=%b,rst=%b,w_add=%d,r_add=%d,we=%b,re=%b,data_in=%d,data_out=%d",clk,rst,w_add,r_add,we,re,data_in,data_out);
endmodule
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