Write Rtl to design a 8x16 asynchronous dual port ram & verify the same.
RTL
// asynchronus dual port ram 8x16
module ram_async8x16(clk,wr_clk,rd_clk,clr,data_in,w_addr,r_addr,we,re,data_out);
parameter depth = 8, width = 16,addr_size=3;
input wr_clk, rd_clk,clk;
input clr;
input we,re;
input [addr_size-1:0]w_addr,r_addr;
input [width-1:0]data_in;
output reg [width-1:0]data_out;
integer i;
reg [width-1:0] mem[depth-1:0];
always@(posedge wr_clk or posedge rd_clk or posedge clk)
begin
if(clr)
begin
for(i=0;i<depth;i=i+1)
begin
mem[i]<=0;
data_out<=0;
end
end
else
begin
if(we)
mem[w_addr]<=data_in;
if(re)
data_out<=mem[r_addr];
end
end
endmodule
Test Bench
// asynchronus dual port ram 8x16 tb
module ram_async8x16_tb();
reg wr_clk, rd_clk,clk,clr;
wire [15:0] data_out;
reg [2:0] w_addr,r_addr;
reg we,re;
reg [15:0] data_in;
ram_async8x16 R(clk,wr_clk,rd_clk,clr,data_in,w_addr,r_addr,we,re,data_out);
initial
begin
clk=0;
forever #5 clk=~clk;
end
initial
begin
wr_clk=0;
forever #20 wr_clk=~wr_clk;
end
initial
begin
rd_clk=0;
forever #40 rd_clk=~rd_clk;
end
task initialize();
begin
we=1'b0;
re=1'b0;
clr=1'b0;
data_in=0;
w_addr=0;
r_addr=0;
end
endtask
task clear;
begin
@(negedge clk)
clr=1'b1;
@(negedge clk)
clr=1'b0;
end
endtask
task write(input w,r, input [2:0]a,input [15:0]b);
begin
@(negedge wr_clk)
begin
we=w;
re=r;
w_addr = a;
data_in = b;
end
end
endtask
task read(input w,r, input [2:0]c);
begin
@(negedge rd_clk)
begin
we=w;
re=r;
r_addr = c;
end
end
endtask
initial
begin
initialize;
clear;
repeat(20)
write(1'b1,1'b0,(({$random}%8)+1'b1),(({$random}%256)+1'b1));
#5;
repeat(20)
read(1'b0,1'b1,({$random}%8));
#500 $finish;
end
initial
$monitor("Values of clk=%b,clr=%b,w_addr=%d,r_addr=%d,we=%b,re=%b,data_in=%d,data_out=%d",clk,clr,w_addr,r_addr,we,re,data_in,data_out);
endmodule
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