Write RTL to design a bidirectional buffer and verify the same using testbench.

  

Write RTL to design a bidirectional buffer and verify the same using testbench.

RTL

// bidirectional  buffer rtl

 

module b_buff(x,y,en);

 

      input en;

      inout x,y;

 

     

      bufif0 T1(y,x,en);

      bufif1 T2(x,y,en);

     

     

endmodule

 

Test Bench

// bidirectional buff testbench

 

module b_buff_tb();

 

      reg en;

      reg a,b;

      wire x,y;

      integer i; 

 

      b_buff B(.x(x),.y(y),.en(en));     

 

      assign x= ~en ? a : 1'bz;

      assign y= en ? b : 1'bz;           

 

 

            initial

                  begin

                        for(i=0;i<8;i=i+1)

                              begin

                                    {a,b,en}=i;

                                    #5;

                              end

                  end

                       

           

            initial

            $monitor("Input a=%b, b=%b, en=%b, Output x=%b, y=%b",a,b,en,x,y);

           

            initial

            #50 $finish;

           

endmodule

 

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