Write Verilog Code for Generate clock With 5 MHz.

  

//generate 5 MHZ signal with 25%duty cycle

 

`timescale 1ns/1ns

 

module c_5mhz();

 

reg clk;

 

initial

begin

    clk=1;

end

 

always@(clk)

begin

    #150 clk=0;

    #50 clk=1;

end

 

initial

$monitor("%d",clk);

 

endmodule

Post Your doubt in mail.👇👇👇

  E-Mail:-denilvaghasiya17@gmail.com