//8:1 mux using for loop RTL
module mux_8x1for(i,s,y);
input [7:0]i;
input [2:0]s;
output reg y;
integer j;
always@(*)
begin
y=0;
for(j=0;j<8;j=j+1)
begin
if(s==j)
y=i[j];
end
end
endmodule
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