To understand how to write RTL abstraction for overlapping sequence ditector 101 using moore fsm.
RTL
//fsm overlapping sequence ditector
module sequence101(clk,rst,seq_in,det_o);
input clk;
input rst;
input seq_in;
output det_o;
parameter idle=2'b00,state1=2'b01,state2=2'b10,state3=2'b11;
reg [1:0]state,next_state;
always@(posedge clk)
begin
if(rst)
state<=idle;
else
state<=next_state;
end
always@(*)
begin
case(state)
idle :
if(seq_in==1)
next_state=state1;
else
next_state=idle;
state1:
if(seq_in==0)
next_state=state2;
else
next_state=state1;
state2:
if(seq_in==1)
next_state=state3;
else
next_state=idle;
state3:
if(seq_in==1)
next_state=state1;
else
next_state=state2;
default : next_state=idle;
endcase
end
assign det_o=(state==state3)? 1'b1:1'b0;
endmodule
Test bench
//fsm overlapping sequence ditector test bench
module sequence101_tb();
reg din,clk,rst;
wire dout;
sequence101 s101(clk,rst,din,dout);
initial
begin
clk=0;
forever #5 clk=~clk;
end
task initialize( );
begin
din = 0;
end
endtask
task reset();
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b0;
end
endtask
task stimulus(input data);
begin
@(negedge clk);
din = data;
end
endtask
initial
begin
initialize;
reset;
stimulus(0);
stimulus(1);
stimulus(0);
stimulus(1);
stimulus(0);
stimulus(1);
stimulus(1);
reset;
stimulus(1);
stimulus(0);
stimulus(1);
stimulus(1);
$finish;
end
initial
$monitor("rst=%b, Din=%b, Output Dout=%b",
rst,din,dout);
endmodule
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