To understand how to write rtl and test bench abstraction for Dff.

  

To understand how to write rtl abstraction for Dff.

RTL

// d flip flop

 

module dflipflop(d,clk,reset,q,q_bar);

 

input d,clk,reset;

output reg q;

output q_bar;

 

always@(posedge clk)

begin

    if(reset)

        q<=0;

    else

        q<=d;

       

end

 

    assign q_bar=~q;

 

 

endmodule

 

Test bench

//dflipflop test bench

 

module dflipflop_tb();

 

reg d,clk,rst;

wire q;

wire q_bar;

parameter CYCLE = 10;

 

dflipflop D(d,clk,rst,q,q_bar);

 

always

    begin

    #(CYCLE/2);

    clk=1'b0;

    #(CYCLE/2);

    clk=1'b1;

    end

/*or--

initial

    begin

    clk=0;

    forever #(CYCLE/2) clk=~clk;

    end

*/

 

 

task reset();

 

begin

    @(negedge clk)

    rst=1'b1;

    @(negedge clk)

    rst=1'b0;

end

 

endtask

 

task data(input a);

begin  

    @(negedge clk)

    d=a;

end

endtask

 

initial

begin

    reset;

    data(1'b0);

   

    data(1'b1);

   

    data(1'b0);

   

    reset;

    data(1'b1);

   

    data(1'b1);

   

    reset;

   

end

 

initial

$monitor("Input d=%b , clk=%b, rst=%b Output q=%b,q_bar=%b",d,clk,rst,q,q_bar);

 

initial

#100 $finish;

 

endmodule

 

 

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