write rtl description and testbench for SR latch using gate level modeling.

  

write rtl description and testbench for SR latch using gate level modeling.

RTL

// SR latch

 

module srlatch(s,r,q,q_bar);

 

input s,r;

inout q,q_bar;

 

nor (q,r,q_bar);

nor (q_bar,s,q);

 

endmodule

 

Test bench

//sr latch tb

 

module srlatch_tb();

 

reg r,s;

wire q,q_bar;

 

srlatch S(s,r,q,q_bar);

 

initial

    begin

    s=1'b1 ; r=1'b0;

    #5 s=1'b0 ; r=1'b0;

    #5 s=1'b0 ; r=1'b1;

    #5 s=1'b0 ; r=1'b0;

    #5 s=1'b1 ; r=1'b1;

    #5 s=1'b0 ; r=1'b0;

    #5;

    end

   

initial

$monitor("Input s=%b,r=%b, Output q=%b, q_bar=%b",s,r,q,q_bar);

 

initial

#40 $finish;

endmodule

 

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