Write RTL description and testbench for 8:3 priority encoder
RTL
//8:3 priority encoder
module encoder8_3(y,d);
input [7:0]y;
output reg [2:0]d;
always@(y)
begin
if(y[7])
d=3'd7;
else if(y[6])
d=3'd6;
else if(y[5])
d=3'd5;
else if(y[4])
d=3'd4;
else if(y[3])
d=3'd3;
else if(y[2])
d=3'd2;
else if(y[1])
d=3'd1;
else if(y[0])
d=3'd0;
else
d=3'd0;
end
endmodule
Test Bench
//8_3 encoder testbech
module encoder8_3_tb();
reg [7:0]y;
wire [2:0]d;
integer i;
encoder8_3 E1(y,d);
task ini();
begin
{y}=0;
end
endtask
task data([7:0]a);
begin
y=a;
end
endtask
initial
begin
ini;
for(i=0;i<256;i=i+1)
begin
data(i);
#5;
end
end
initial
$monitor("Input y=%b, Output d=%b",y,d);
initial
#1500 $finish;
endmodule
Post Your doubt in mail.👇👇👇
E-Mail:-denilvaghasiya17@gmail.com
0 Comments