Write Rtl to design a clock buffer & verify the same usinf test bench.

  

Write Rtl to design a clock buffer & verify the same.

RTL

//write rtl design for clock buffer

 

 

module clock_buff(m_clk,b_clk);

 

input m_clk;

output b_clk;

 

buf CB(b_clk,m_clk);

 

endmodule

 

Test Bench

//write rtl design for clock buffer test bench

 

`timescale 1ns/1ns

 

module clock_buff_tb();

 

reg m_clk;

integer t1,t2,t3,t4,t5,t6;

wire b_clk;

real phasediff,freq_m_clk,freq_b_clk;

 

clock_buff D(m_clk,b_clk);

 

initial

    begin

        m_clk=0;

        forever #20 m_clk=~m_clk;

    end

   

task initialize;

begin

        {m_clk,t1,t2,t3,t4,t5,t6}=0;

end

endtask

 

task pd();

fork

    @(posedge m_clk)

        t1=$time;

    @(posedge b_clk)

        t2=$time;

assign phasediff=t2-t1;

join

endtask

   

task m();

begin

    @(posedge m_clk)

        t3=$time;

    @(posedge m_clk)

        t4=$time;

assign freq_m_clk=1.0/(t4-t3);

end

endtask

 

task b();

begin

    @(posedge b_clk)

        t5=$time;

    @(posedge b_clk)

        t6=$time;

assign freq_b_clk=1.0/(t6-t5);

end

endtask

 

initial

    fork

        initialize;

        pd;

        m;

        b;

    join

   

 

 

initial

$monitor("Input m_clk=%d,b_clk=%d,t1=%t,t2=%t,t3=%t,t4=%t ,t5=%t,t6=%t,phasediff=%t,freq_m_clk=%g,freq_b_clk=%g",m_clk,b_clk,t1,t2,t3,t4,t5,t6,phasediff,freq_m_clk,freq_b_clk);

 

initial

#200 $finish;

 

endmodule

 

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