Write an RTL code for a 4-bit SIPO(serial-in-parallel-out)shift register which shifts first 2-bits (shift for 2 times) to left/right and should shift for 2 more times which should have the previous value.

  /*Write an RTL code for a 4-bit SIPO(serial-in-parallel-out)shift register which shifts first 2-bits (shift for 2 times) to

left/right and should shift for 2 more times which should have the previous value.*/ module sipo(clk,rst,si,q1); input clk,rst; input si; reg signed [3:0]q; output [3:0]q1; always@(posedge clk) begin if(rst) q<=4'b0000; else begin q[3]<=si; q[2]<=q[3]; q[1]<=q[2]; q[0]<=q[1]; end end assign q1=q>>>2; endmodule

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