All part --> part 1 part 2 part 3 part 4 part 5 final
Real Time Alarm Clock
For Design The functionality of alarm clock We need to Require 6 diffrent module.
Think for Digital Wrist watch
Time Generator
rst high One second and one minute is going to zero.
same for
rst count is high One minute and one second pulse is zero.
we use rst count lets say your time at 11:30 and between 11:31 your reset count is 1 then it start from o second .
if fast watch is high
One minute pulse we get at 256 clk same time as one second this signal we use for fast verification only
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RTL
//Timing generator
module TimingGen(clk,rst,rst_count,fast_watch,one_minute,one_second);
input clk,rst,rst_count,fast_watch;
output reg one_minute,one_second;
reg [13:0]count_min;
reg [7:0]count_sec;
reg one_minute_temp;
always@(posedge clk)
begin
if(rst)
begin
count_sec<=0;
one_second<=0;
end
else if(rst_count)
begin
count_sec<=0;
one_second<=0;
end
else
begin
if(count_sec==255)
begin
count_sec<=0;
one_second<=1;
end
else
begin
count_sec<=count_sec+1;
one_second<=0;
end
end
end
always@(posedge clk)
begin
if(rst)
begin
count_min<=0;
one_minute_temp<=0;
end
else if(rst_count)
begin
count_min<=0;
one_minute_temp<=0;
end
else
begin
if(count_min==15359)
begin
count_min<=0;
one_minute_temp<=1;
end
else
begin
count_min<=count_min+1;
one_minute_temp<=0;
end
end
end
always@(posedge clk)
begin
if(fast_watch)
one_minute<=one_second;
else
one_minute<=one_minute_temp;
end
endmodule
//Timing generator test bench
`timescale 1ms/1us
module TimingGen_tb();
reg clk,rst,rst_count,fast_watch;
wire one_minute,one_second;
TimingGen TG(clk,rst,rst_count,fast_watch,one_minute,one_second);
initial
begin
clk=0;
forever #1.953125 clk=~clk;
end
task initialize();
begin
{clk,rst,rst_count,fast_watch}=0;
end
endtask
task reset();
begin
@(negedge clk)
rst=1;
@(negedge clk)
rst=0;
end
endtask
task reset_count();
begin
@(negedge clk)
rst_count=1;
@(negedge clk)
rst_count=0;
end
endtask
task fast(input a);
begin
@(negedge clk)
fast_watch=a;
end
endtask
initial
begin
initialize;
reset;
fast(1);
repeat(255)
begin
@(negedge clk);
end
fast(0);
reset;
repeat(15370)
@(negedge clk)
#5;
end
initial
$monitor($time,"Input
clk=%b,rst=%b,rst_count=%b,fast_watch=%b Output
one_minute=%b,one_second=%b",clk,rst,rst_count,fast_watch,one_minute,one_second);
initial
#61100 $finish;
endmodule
Logic
|
BCD |
ASCII |
|
0000 |
‘h30 |
|
0001 |
‘h31 |
|
0010 |
‘h32 |
|
0011 |
‘h33 |
|
0100 |
‘h34 |
|
0101 |
‘h35 |
|
0110 |
‘h36 |
|
0111 |
‘h37 |
|
1000 |
‘h38 |
|
1001 |
‘h39 |
//lcd display driver
module LCDdriver(show_a,show_new_time,alarm_time,current_time,key,sound_alarm,display_time);
input show_a,show_new_time;
input [3:0]alarm_time,current_time,key;
output reg sound_alarm;
output reg [7:0]display_time;
reg [3:0]display_value;
always@(*)
begin
if(show_new_time)
display_value=key;
else if(show_a)
display_value=alarm_time;
else
display_value=current_time;
if(current_time==alarm_time)
sound_alarm=1'b1;
else
sound_alarm=1'b0;
end
always@(display_value)
begin
case(display_value)
4'b0000 : display_time=8'h30;
4'b0001 : display_time=8'h31;
4'b0010 : display_time=8'h32;
4'b0011 : display_time=8'h33;
4'b0100 : display_time=8'h34;
4'b0101 : display_time=8'h35;
4'b0110 : display_time=8'h36;
4'b0111 : display_time=8'h37;
4'b1000 : display_time=8'h38;
4'b1001 : display_time=8'h39;
default : display_time=8'h00;
endcase
end
endmodule
//lcd display driver test bench
module LCDdriver_tb();
reg show_a,show_new_time;
reg [3:0]alarm_time,current_time,key;
wire [7:0]display_time;
wire sound_alarm;
LCDdriver LD(show_a,show_new_time,alarm_time,current_time,key,sound_alarm,display_time);
initial
begin
show_a=0;
show_new_time=0;
alarm_time=0;
current_time=0;
key=0;
end
initial
begin
show_a=1;
show_new_time=0;
alarm_time=4'd5;
current_time=4'd6;
key=4'd7;
#10;
show_a=0;
show_new_time=1;
alarm_time=4'd5;
current_time=4'd6;
key=4'd7;
#10;
show_a=0;
show_new_time=1;
alarm_time=4'd5;
current_time=4'd5;
key=4'd7;
#10;
show_a=1;
show_new_time=1;
alarm_time=4'd5;
current_time=4'd5;
key=4'd7;
#10;
show_a=0;
show_new_time=0;
alarm_time=4'd5;
current_time=4'd5;
key=4'd7;
#10;
show_a=1;
show_new_time=0;
alarm_time=4'd12;
current_time=4'd5;
key=4'd7;
end
initial
$monitor("Input
show_a=%b,show_new_time=%b,alarm_time=%d,current_time=%d,key=%d Output
sound_alarm=%b,display_time=%h",show_a,show_new_time,alarm_time,current_time,key,sound_alarm,current_time);
initial
#100 $finish;
endmodule
________________________Continue With display drive
//display driver rtl
module displayDriver(current_time_ms_hr,current_time_ms_min,current_time_ls_hr,current_time_ls_min,
alarm_time_ms_hr,alarm_time_ms_min,alarm_time_ls_hr,alarm_time_ls_min,
key_ms_hr,key_ms_min,key_ls_hr,key_ls_min,
show_a,show_new_time,
sound_alarm,
display_ms_hr,display_ms_min,display_ls_hr,display_ls_min);
input show_a,show_new_time;
input [3:0]current_time_ms_hr,current_time_ms_min,current_time_ls_hr,current_time_ls_min,
alarm_time_ms_hr,alarm_time_ms_min,alarm_time_ls_hr,alarm_time_ls_min,
key_ms_hr,key_ms_min,key_ls_hr,key_ls_min;
output sound_alarm;
wire sound_alarm1,sound_alarm2,sound_alarm3,sound_alarm4;
output [7:0]display_ms_hr,display_ms_min,display_ls_hr,display_ls_min;
LCDdriver D1(show_a,show_new_time,alarm_time_ms_hr,current_time_ms_hr,key_ms_hr,sound_alarm1,display_ms_hr);
LCDdriver D2(show_a,show_new_time,alarm_time_ms_min,current_time_ms_min,key_ms_min,sound_alarm2,display_ms_min);
LCDdriver D3(show_a,show_new_time,alarm_time_ls_hr,current_time_ls_hr,key_ls_hr,sound_alarm3,display_ls_hr);
LCDdriver D4(show_a,show_new_time,alarm_time_ls_min,current_time_ls_min,key_ls_min,sound_alarm4,display_ls_min);
assign sound_alarm=(sound_alarm1 & sound_alarm2 & sound_alarm3 & sound_alarm4);
endmodule
TEST BENCH
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