Write RTL description and test bench for 3:8 decoder

  

Write RTL description and test bench for 3:8 decoder

RTL

//3:8 decoder

 

 

module decoder3_8(d,y);

 

input [2:0]d;

output reg [7:0]y;

 

always@(d)

begin

case(d)

 

3'b000 : y=8'b00000001;

3'b001 : y=8'b00000010;

3'b010 : y=8'b00000100;

3'b011 : y=8'b00001000;

3'b100 : y=8'b00010000;

3'b101 : y=8'b00100000;

3'b110 : y=8'b01000000;

3'b111 : y=8'b10000000;

 

default : y=8'b00000000;

 

endcase

end

endmodule

 

 

Test Bench

//3:8 decoder test bench

 

module decoder3_8_tb();

 

wire [7:0]y;

reg [2:0]d;

integer i;

 

decoder3_8 D1(d,y);

 

task ini();

      begin

            d=3'b000;

      end

endtask

 

task data([2:0]a);

      begin

            d=a;

      end

endtask

 

initial

      begin

            ini;

            for(i=0;i<8;i=i+1)

            begin

                  data(i);

                  #5;

            end

            #5;

      end

 

initial

$monitor("Input d=%b, Output y=%b",d,y);

 

initial

#100 $finish;

 

endmodule

 

 

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