write rtl description and testbench for Jk flipflop using parameter declaration for the respective scenario(Hold,toggle,set,reset).

  

write rtl description and testbench for Jk flipflop using parameter declaration for the

respective scenario(Hold,toggle,set,reset).

RTL

// j k flipflop

 

module jkflipflop(j,k,clk,rst,q,q_bar);

 

input j,k,rst,clk;

output reg q;

output q_bar;

 

parameter nochange=2'b00;

parameter set=2'b01;

parameter reset=2'b10;

parameter toggle=2'b11;

 

assign q_bar=~q;

 

always@(posedge clk)

begin

 

if(rst)

    q<=0;

else

 

case({j,k})

 

 

nochange : q<=q;

set : q<=1'b1;

reset : q<=1'b0;

toggle : q<=q_bar;

 

 

endcase

 

end

endmodule

 

Test bench

//jk test bench

 

module jkflipflop_tb();

reg j,k,clk,rst;

wire q,q_bar;

 

jkflipflop JK(j,k,clk,rst,q,q_bar);

 

initial

 

begin

clk=0;

forever #5 clk=~clk;

end

 

initial

begin

rst=0;

#5 j=1; k=0;

#5 j=0; k=0;

#5 j=0; k=1;

#5 j=1; k=1;

#5 j=1; k=1;

#5;

rst=1;

#5 j=1; k=0;

#5 j=0; k=0;

#5;

 

end

 

initial

$monitor("Input rst=%b,clk=%b,j=%b,k=%b Output q=%b,q_bar=%b",rst,clk,j,k,q,q_bar);

 

initial

#50 $finish;

 

endmodule

 

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