Write Rtl to design a 4 bit right shift serial in serial out(SISO) shift register & verify the same using test bench.

Write Rtl to design a 4 bit right shift serial in serial out shift register & verify the same.

RTL

// 4bit right bit shift registor

module siso(clk,rst,si,so);

input si;

input clk,rst;

output so;

reg [3:0]q;

always@(posedge clk)

begin

if(rst)

q<=4'd0;

else

begin

q[3]<=si;

q[2]<=q[3];

q[1]<=q[2];

q[0]<=q[1];

end

assign so=q[0];

endmodule

Test Bench

// 4bit right bit shift registor test benvh

module siso_tb();

reg si;

reg clk,rst;

wire so;

siso SR(clk,rst,si,so);

initial

begin

clk=0;

forever #5 clk=~clk;

end

task initialize;

begin

si=0;

end

endtask

task reset;

begin

@(negedge clk)

rst=1'b1;

@(negedge clk)

rst=1'b0;

end

endtask

task serialinput(input a);

begin

@(negedge clk)

si=a;

end

endtask

initial

begin

initialize;

reset;

serialinput(1);

#5;