Real Time Alarm clock project (part 5)

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6> Controller

This part is heart of the project

It will controlle all modul. base on this we have to decide how mush time if we hold key then it reset or etc base on FSM.

Here is fsm Base on that you need to work 

If you dont understand the fsm then try to under stand key==10 mans we dont give any key

RTL

// moore fsm for Alarm controller

 

module controller(clk,rst,alarm_button,time_button,key,one_sec,load_new_c,show_new_time,show_a,load_new_a,shift,rst_count);

 

input clk,rst,alarm_button,time_button,one_sec;

input [3:0]key;

 

output load_new_c,show_new_time,show_a,load_new_a,shift,rst_count;

 

parameter show_time=3'b000,

            key_stored=3'b001,

            key_waited=3'b010,

            key_entry=3'b011,

            set_alarm_time=3'b100,

            set_current_time=3'b101,

            show_alarm=3'b110;

           

reg [3:0]count1; //10sec for key_waited

reg [3:0]count2; //10sec for key_entry         

 

reg [2:0]state,next_state;

wire time_out;

 

always@(posedge clk)

begin

    if(rst)

    state<=show_time;

   

    else

    state<=next_state;

end

 

always@(posedge clk)

begin

    if(rst)

        count1<=0;

   

    else if(!(state==key_waited))

        count1<=0;

    else if(count1==9)

        count1<=0;

    else if(one_sec)

        count1<=count1+1;

       

end

 

always@(posedge clk)

begin

    if(rst)

        count2<=0;

   

    else if(!(state==key_entry))

        count2<=0;

    else if(count2==9)

        count2<=0;

    else if(one_sec)

        count2<=count2+1;

       

end

 

assign time_out=(count1==9 || count2==9) ? 1'b0 : 1'b1;

 

 

 

always@(*)

begin  

    case(state)

   

    show_time : begin

                if(alarm_button)

                next_state=show_alarm;

                else if(key!=10)

                next_state=key_stored;

                else

                next_state=show_time;

                end

               

    key_stored : next_state=key_waited;

                   

    key_waited : begin

                 if(key==10)

                    next_state=key_entry;

                 else if(time_out==0)

                    next_state=show_time;

                 else

                    next_state=key_waited;

                 end

    key_entry : begin

                if(alarm_button)

                    next_state=set_alarm_time;

                else if(time_button)

                    next_state=set_current_time;

                else if(time_out==0)

                    next_state=show_time;

                else if(key!=10)

                    next_state=key_stored;

                else

                    next_state=key_entry;

                end

               

    set_alarm_time : next_state=show_time;

   

    set_current_time : next_state=show_time;

   

    show_alarm : begin

                 if(!alarm_button)

                    next_state=show_time;

                 else

                    next_state=show_alarm;

                 end

                

    default next_state=show_time;

    endcase

end

 

assign show_a=(state==show_alarm) ? 1'b1 : 1'b0;

assign show_new_time=(state==key_entry || state==key_stored || state==key_waited) ? 1'b1 : 1'b0;

assign load_new_a=(state==set_alarm_time)? 1'b1 : 1'b0;

assign load_new_c=(state==set_current_time)? 1'b1 : 1'b0;

assign rst_count =(state==set_current_time)? 1'b1 : 1'b0;

assign shift=(state==key_stored)? 1'b1 : 1'b0;

 

 

endmodule

                   

TEST BENCH

//fsm test bench module controller_tb(); reg clk,rst,alarm_button,time_button,one_sec; reg [3:0]key; wire load_new_c,show_new_time,show_a,load_new_a,shift,rst_count; controller CR(clk,rst,alarm_button,time_button,key,one_sec,load_new_c,show_new_time,show_a,load_new_a,shift,rst_count); initial begin clk=0; forever #1 clk=~clk; end task initialize(); begin {clk,rst,alarm_button,time_button,one_sec,key}=0; end endtask task reset(); begin @(negedge clk) rst=1; @(negedge clk) rst=0; end endtask task data(input [3:0]d); begin key=d; end endtask task alarm_b(input a); begin alarm_button=a; end endtask task time_b(input t); begin time_button=t; end endtask task ONE(input o); begin one_sec=o; end endtask initial begin initialize; reset; data(4'd0); repeat(3) @(negedge clk); data(4'd10); @(negedge clk); data(4'd3); repeat(3) @(negedge clk); data(4'd10); @(negedge clk); data(4'd3); repeat(3) @(negedge clk); data(4'd10); @(negedge clk); data(4'd0); repeat(3) @(negedge clk); data(4'd10); @(negedge clk); time_b(1); @(negedge clk); time_b(0); //------------------------ end initial $monitor($time,"Input clk=%b,rst=%b,alarm_button=%b,time_button=%b,key=%b,one_sec=%b Output load_new_c=%b,show_new_time=%b,show_a=%b,load_new_a=%b,shift=%b,rst_count=%b",clk,rst,alarm_button,time_button,key,one_sec,load_new_c,show_new_time,show_a,load_new_a,shift,rst_count); initial #5000 $finish; endmodule _---------->Continue to final module final