Real Time alarm clock project(Part 4)

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5>Key Register

Key register is use for give key 

like this Your current time is 

    12:30

now you give key to set new time then this way you key is shift

let me set to 10:20

1st    -->         23:01            1

2nd   -->         30:10            0

3rd   -->          01:02            2

4th   -->          10:20            0          

RTL   

//key register module keyreg(clk,rst,key,shift,key_buffer_ms_hr,key_buffer_ls_hr,key_buffer_ms_min,key_buffer_ls_min); input clk,rst,shift; input [3:0]key; output reg [3:0]key_buffer_ms_hr,key_buffer_ls_hr,key_buffer_ms_min,key_buffer_ls_min; always@(posedge clk) begin if(rst) begin key_buffer_ms_hr<=0; key_buffer_ls_hr<=0; key_buffer_ms_min<=0; key_buffer_ls_min<=0; end else if(shift) begin key_buffer_ls_min<=key; key_buffer_ms_min<=key_buffer_ls_min; key_buffer_ls_hr<=key_buffer_ms_min; key_buffer_ms_hr<=key_buffer_ls_hr; end else begin key_buffer_ls_min<=key_buffer_ls_min; key_buffer_ms_min<=key_buffer_ms_min; key_buffer_ls_hr<=key_buffer_ls_hr; key_buffer_ms_hr<=key_buffer_ms_hr; end end endmodule

TEST BENCH

//key register test bench module keyreg_tb(); reg clk,rst,shift; reg [3:0]key; wire [3:0]key_buffer_ms_hr,key_buffer_ls_hr,key_buffer_ms_min,key_buffer_ls_min; keyreg KR(clk,rst,key,shift,key_buffer_ms_hr,key_buffer_ls_hr,key_buffer_ms_min,key_buffer_ls_min); initial begin clk=0; forever #5 clk=~clk; end task initialize(); begin {clk,rst,key,shift}=0; end endtask task reset(); begin @(negedge clk) rst=1; @(negedge clk) rst=0; end endtask task data(input [3:0]a); begin @(negedge clk) key=a; end endtask task shifting(input b); begin shift=b; end endtask initial begin initialize; reset; shifting(1); data(4'd1); data(4'd2); data(4'd5); data(4'd9); #10; shifting(0); #40; shifting(1); data(4'd0); data(4'd9); data(4'd4); data(4'd3); #10; end initial $monitor($time,"Input clk=%b,rst=%b,key=%b,shift=%b Output key_buffer_ms_hr=%b,key_buffer_ls_hr=%b,key_buffer_ms_min=%b,key_buffer_ls_min=%b",clk,rst,key,shift,key_buffer_ms_hr,key_buffer_ls_hr,key_buffer_ms_min,key_buffer_ls_min); initial #155 $finish; endmodule

___________---> Continue To part 5 part 5