Real Time alarm clock project(Part 3)

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4>Counter

Counter count for 0-9 depend on min and hr

as we know 

       2                3                :                5                        9

    ms-hr        ls-hr                              ms-min            ls-min

logic;

   if ls min 9 then ls min=0, and ms-min=+1;

    other wise ls-min=+1;    

if ms-min=5 then ms-min=0 and ls-hr =+1;

if ls-hr =3 then ms-hr=+1;

if ms-hr==2 ls-hr ==3 ms-min==5 ls-min==9 then all==0

See RTL for better understanding

RTL

//counter module counter(clk,rst,one_minute,load_new_c, new_current_time_ms_hr,new_current_time_ls_hr,new_current_time_ms_min,new_current_time_ls_min, current_time_ms_hr,current_time_ls_hr,current_time_ms_min,current_time_ls_min); input clk,rst,one_minute,load_new_c; input [3:0]new_current_time_ms_hr,new_current_time_ls_hr,new_current_time_ms_min,new_current_time_ls_min; output reg [3:0]current_time_ms_hr,current_time_ls_hr,current_time_ms_min,current_time_ls_min; always@(posedge clk) begin if(rst) begin current_time_ms_hr<=0; current_time_ls_hr<=0; current_time_ms_min<=0; current_time_ls_min<=0; end else if(load_new_c) begin current_time_ms_hr<=new_current_time_ms_hr; current_time_ls_hr<=new_current_time_ls_hr; current_time_ms_min<=new_current_time_ms_min; current_time_ls_min<=new_current_time_ls_min; end else if(load_new_c==0 && one_minute==0) begin current_time_ms_hr<=current_time_ms_hr; current_time_ls_hr<=current_time_ls_hr; current_time_ms_min<=current_time_ms_min; current_time_ls_min<=current_time_ls_min; end else if(load_new_c==0 && one_minute==1) begin if(current_time_ls_min==9) begin current_time_ls_min<=0; current_time_ms_min<=current_time_ms_min+1; end else current_time_ls_min<=current_time_ls_min+1; if(current_time_ms_min==5 && current_time_ls_min==9) begin current_time_ms_min<=0; current_time_ls_min<=0; current_time_ls_hr<=current_time_ls_hr+1; end if(current_time_ls_hr==9 && current_time_ms_min==5 && current_time_ls_min==9) begin current_time_ls_hr<=0; current_time_ms_min<=0; current_time_ls_min<=0; current_time_ms_hr<=current_time_ms_hr+1; end if(current_time_ms_hr==2 && current_time_ls_hr==3 && current_time_ms_min==5 && current_time_ls_min==9) begin current_time_ms_hr<=0; current_time_ls_hr<=0; current_time_ms_min<=0; current_time_ls_min<=0; end end end endmodule TEST BENCH

//counter test bench

 

module counter_tb();

 

reg clk,rst,one_minute,load_new_c;

reg [3:0]new_current_time_ms_hr,new_current_time_ls_hr,new_current_time_ms_min,new_current_time_ls_min;

 

wire [3:0]current_time_ms_hr,current_time_ls_hr,current_time_ms_min,current_time_ls_min;   

 

counter C(clk,rst,one_minute,load_new_c,

                new_current_time_ms_hr,new_current_time_ls_hr,new_current_time_ms_min,new_current_time_ls_min,

                current_time_ms_hr,current_time_ls_hr,current_time_ms_min,current_time_ls_min);

   

initial

begin

    clk=0;

    forever #5 clk=~clk;

end

 

 

task initialize();

begin

    {clk,rst,one_minute,load_new_c,

                new_current_time_ms_hr,new_current_time_ls_hr,new_current_time_ms_min,new_current_time_ls_min}=0;

end

endtask

 

task reset();

begin

    @(negedge clk)

    rst=1;

    @(negedge clk)

    rst=0;

end

endtask

 

task data(input [3:0]a,b,c,d);

begin

    @(negedge clk)

    load_new_c=1;

    one_minute=0;

    new_current_time_ms_hr=a;

    new_current_time_ls_hr=b;

    new_current_time_ms_min=c;

    new_current_time_ls_min=d;

    @(negedge clk)

    load_new_c=0;

    one_minute=1;

end

endtask

 

task mini(input e);

begin

    one_minute=e;

end

endtask

 

initial

begin

    initialize;

    reset;

   

    data(4'd0,4'd1,4'd1,4'd0);

    #5;

end

 

initial

$monitor($time,"Input clk=%b,rst=%b,one_minute=%b,load_new_c=%b,new_current_time_ms_hr=%b,new_current_time_ls_hr=%b,new_current_time_ms_min=%b,new_current_time_ls_min=%b Outputcurrent_time_ms_hr=%b,current_time_ls_hr=%b,current_time_ms_min=%b,current_time_ls_min=%b",clk,rst,one_minute,load_new_c,new_current_time_ms_hr,new_current_time_ls_hr,new_current_time_ms_min,new_current_time_ls_min,current_time_ms_hr,current_time_ls_hr,current_time_ms_min,current_time_ls_min);

 

initial

#20000 $finish;

 

endmodule

--------------->Continue Part 4part 4