VerilogHDL
Write an RTL code for a 4-bit SIPO(serial-in-parallel-out)shift register which shifts first 2-bits (shift for 2 times) to left/right and should shift for 2 more times which should have the previous value.
/*Write an RTL code for a 4-bit SIPO(serial-in-parallel-out)shift register w…
Read more
VerilogHDL
Write RTL for 8x1 Mux using For loop.
//8:1 mux using for loop RTL module mux_8x1for ( i , s , y ); input […
Read more
VerilogHDL
Write Verilog Code for Generate clock With 5 MHz.
//generate 5 MHZ signal with 25%duty cycle `timescale 1ns / 1ns module…
Read more
VerilogHDL
Write Verilog Code for Generate clock With 2 GHz.
//generate 2 GHZ signal with 75%duty cycle `timescale 1ps / 1ps module…
Read more
VerilogHDL
Write Verilog Code for Generate clock With 256 Hz.
//generate 256HZ signal with 50 %duty cycle `timescale 1ms / 1us modul…
Read more
VerilogHDL
Write RTL for real 5 random number between 2-5 with 3 point precision.
//real 5 random number between 2-5 with 3 point precision module randreal …
Read more
VerilogHDL
Write RTL And Test bench For gated sr latch.
RTL //gated latch module gatedlatch ( s , r , ctr , q , q_bar ); input …
Read more
Social Plugin